Method of a semiconductor device wherein film cracking is prevented by formation of a glass layer

ABSTRACT

IN THEMANUFACTURE OF A SEMICONDUCTOR DEVICE WHEREIN A FILM IS TO BE FORMED OVER PORTIONS OF A FIRST LAYER HAVING ABRUPT SURFACE CONTOURS, THE IMPROVEMENT OF FORMING A GLASS LAYER, HAVING A MELTING POINT LOWER THAN THAT OF SAID FIRST LAYER, ON THE FIRST LAYER AND HEATING SUFFICIENTLY TO CAUSE A PLASTIC FLOW OF THE GLASS LAYER AT THE ABRUPT CONTOUR TO ROUND THE EDGES AND AVOID CRACKING OF THE SUBSEQUENTLY ESTTABLISH FILM.

July 23, 1974 e. E. MOORE METHOD OF A SEMICONDUCTOR DEVICE WHEREIN FILMCRACKING IS PREVENTED BY FORMATION OF A GLASS LAYER Ori inal Filed Jan22 1970 GORDON E MOORE INVEN'TUR.

BY a% United States Patent Int. Cl. H011 7/34 US. Cl. 117-212 19 ClaimsABSTRACT OF THE DISCLOSURE In the manufacture of a semiconductor devicewherein a film is to be formed over portions of a first layer havingabrupt surface contours, the improvement of forming a glass layer,having a melting point lower than that of said first layer, on the firstlayer and heating sufficiently to cause a plastic flow of the glasslayer at the abrupt contour to round the edges and avoid cracking of thesubsequently established film.

This is a continuation of application Ser. No. 4,841, filed Jan. 22,1970, now abandoned.

BACKGROUND OF THE INVENTION (1) Field of the Invention This inventionrelates to the field of semiconductor devices such as integratedcircuits.

(2) Prior Art In the manufacture of miniature electronic devices such assemiconductor integrated circuits, it is frequently desired to establishelectrical interconnections between two parts of the device by means ofa conductive film making contact to the parts to be interconnected.Typically, this conducting film has a portion that overlies aninsulating film and makes contact through small apertures in theinsulator (e.g. silicon dioxide) to the underlying device portion (e.g.silicon). In addition, it is often desirable that this conducting filmcross other films, which might be conducting, insulating orsemiconducting. To accomplish this, conductive film (e.g. aluminum) isvacuum evaporated or otherwise deposited atop the device structure andphotoengraved to leave a desired pattern of conductors.

The sequential film-forming and photoengraving processes utilized toconstruct the underlying device structure generally result in theoccurrence of variations of height, comparable to the thicknesses of thefilms involved. Certain of these changes in surface elevation can havevery steep, or even overhanging edges. These edges act asstress-concentrating regions and can result in occurrence of cracks inthe conducting film that must traverse them. Such cracks are extremelydeleterious. They can cause low production yield and can result inproducts that have high rates of failure in use.

Generally in the prior art, an attempt to minimize the occurrence ofsuch cracks has involved an attempt to minimize the height of such stepsby variation of the thickness of the several films or by makingtransitions through several levels of terraces, or an attempt to obtaingradual slopes through etching procedures. Both terracing andetch-sloping consume significant area in the structure, which is costly.Often the thicknesses of film required for acceptable step height isincompatible with the circuit requirements.

This metal cracking problem is particularly acute in the fabrication ofsilicon-gate field effect integrated circuits, due to the requirement ofrelatively thick insulator films and the desire to cross silicon stripscovered with insulators with metallic conductors. In silicon-gatedevices 3,825,442 Patented July 23, 1974 ice the gate electrode isfabricated with polycrystalline silicon instead of aluminum as inmetal-oxide-silicon devices, thereby resulting in greater switchingspeeds and lower threshold voltages. Another advantage which accruesduring fabrication of the silicon-gate structure is self-alignment ofthe gate with the drain and source. These and other advantages result ina size reduction capability on the order of 50% for silicon-gateintegrated circuits, as compared with conventional MOS integratedcircuits, thereby allowing more circuit elements to be formed on asingle semiconductor chip and intensifying contact reliability problemsdue to cracking of the conductive films. The present invention isdirected toward increasing the reliability and production yield ofintegrated circuit devices by providing a simple and effective solutionto the aforementioned metal cracking problem.

SUMMARY OF THE INVENTION The present invention technique is applicablein the fabrication of a semiconductor device wherein an insulating,protective or passivating layer (e.g. silicon oxide) is established onthe surface of a body of semiconductor material, the layer having abruptcontours such as an aperture therethrough to expose a portion of thesemiconductor surface to which it is desired to establish an electricalcontact. The electrical contact is formed by a conductive filmcontacting the exposed semiconductor surface and overlying portions ofthe protective layer. Briefly, the invention comprises heating theoverlying protective layer prior to forming the conductive film, in thepresence of a glass former having a melting point lower than that of theprotective layer (e.g. silicon oxide), sufficiently to form a glasslayer on the protective layer and to cause plastic flow of the glass atthe abrupt surface contours to round off or dull the sharp edges andeliminate the stress points which would cause a cracking tendency uponsubsequent formation of the metallic film.

The glass layer can be formed by depositing the glass former on theprotective layer prior to heating, by heating the protective layer in anatmosphere containing atoms of the glass former, or by forming a dopedglass layer on the protective layer prior to formation of the apertures.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial cross-sectionview, in elevation of a film member on a substrate with a depositedlayer thereover.

FIG. 2 is a partial cross-section view of the film member and layerthereover after employing one embodiment of the invention.

FIG. 3 is a partial cross-section view, in elevation, of a silicon-gatefield effect transistor fabricated in accordance with prior arttechniques.

FIG. 4 is a partial cross-section view, in elevation, of a silicon-gatefield effect transistor in an intermediate stage of production inaccordance with prior art techniques.

FIG. 5 shows the device of FIG. 4 in a subsequent stage of production inaccordance with the present invention technique.

FIG. 6 shows the completed device.

DESCRIPTION OF THE PREFERRED EMBODIMENT Broadly, the invention involvesan insulator layer for micro electronic applications wherein theinsulator readily acepts or includes (e.g. inheretly or by addition) aglass former and forms a glass at a low melting temperature relative tothe melting point of a conductor or other circuit element formedadjacent the insulator. In forming the glass, abrupt contours of theinsulator are rounded or smoothed to form gradual surface transitions.This concept is generally shown in FIGS. 1 and 2. In FIG. 1, there isshown a substrate 1 having a surface 2 receiving a circuit component 3.The circuit component 3 may take the form of a resistor, conductor,interconnect, gate, active element or other components. Deposited overthe component 3 is an insulator or passivating layer 4 which may be anylayer that accepts a glass forming material to form a low melting glasssuch as silicon dioxide. When the insulator 4 is pyrolytically depositedover a component 3, the insulator layer 4 often forms a mushroom likeprotrusion or surface contour 5. It should be readily apparent that itis most difiicult to deposit another film over such a surface. Anattempt to form another film thereover is likely to result in a crackingproblem. To avoid this problem, prior to the deposition of a film overinsulator layer 4, the insulator layer is heated to form a glass. Theglass must be formed at a temperature which does not substantiallyaffect component 3 or substrate 1. The glass may be formed by theaddition of a glass former to the insulator layer 4 or by forming theinsulator 4 with a glass former therein. It may also be possible to outdiffuse a glass former from the substrate 1 or component 3.

It has been found that once the glass former has become a part ofinsulator 4, the heating to form the glass will result in a changing ofthe surface contour in a manner similar to that shown in FIG. 2. It canbe seen that the mushroom-like protrusion 5 has been greatly minimizedand contours have been formed that are compatible with the deposition orforming of another layer over the insulator 4. It has been found thatthis step of heating to form a glass minimizes the cracking problem andimproves reliability and yield.

The present invention technique will now be described with reference tothe fabrication of a silicon-gate field effect transistor, which may bea part of an integrated circuit formed on a silicon chip, although it isunderstood that the disclosed technique is applicable in the fabricationof any semiconductor device wherein a conductive metallic, or other thinfilm is to be established covering abrupt surfaces or apertured portionsof a layer.

Turning first to FIG. 3, a typical silicon gate field effect transistoris shown, employing a silicon substrate having a source electrode and adrain electrode 16 diffused into upper surface 11. Gate oxide 21 isgrown prior to deposition of a polycrystalline silicon gate electrode20, and a silicon dioxide layer 25 is etched away to form aperturesexposing portions of the upper surface of the substrate 10 so that thesource and drain regions may be formed by a diffusion step. An oxidefilm is then deposited over the entire surface of the substrate. Theopenings are then etched in the oxide to permit connection to the sourceand drain. A conductive film 30 (e. g. polycrystalline silicon) isformed over at least a portion of the source region 15, and coveringparts of the exposed semiconductor surface areas and adjacent portionsof layer 25. Likewise, a conductive film 31 is formed over the drainregion 16. This type of structure and various methods for forming it areWell known in the art and hence will not be discussed in greater detail.

The films 30 and 31 are subject to cracking (as indicated by the arrows)at stress points formed by the relatively sharp aperture edges definedby the etched away portions of the layer 25, this cracking tendencybeing a disadvantageous feature of the illustrated prior art structure.

FIGS. 4-6 depict the present invention fabrication technique, with FIG.4 showing the prior art structure of FIG. 3 before metalizing, with likereference numerals indicating similar structure throughout. It is atthis point in the device fabrication that the present inventiontechnique may depart from the prior art fabrication technique.

The next process step is to establish on the silicon oxide (insulating)layer 25, a covering glass layer such as a phosphorus doped siliconoxide having a lower melting point than the underlying component and theformed insulating layer. To establish this glass layer any glass former(e.g. phosphorus, boron, zinc, lead) having a melting point lower thanthat of the insulating layer and the underlying component can beutilized. Should such a glass former be present as a result of a priorfabrication step then merely heating will suffice to form the desiredglass layer. Otherwise, the glass former must be introduced, such as bypyrolytic deposition of a dopant. It should be understood that theinsulating layer and glass former should be selected to form acompatible system and that it is not necessary to add a glass former tocertain systems. For example, arsenic sulfide requires no additionalglass former but functions as an insulating layer and forming a glasswhen heated. Certain halides (e.g. a, Na, K etc.) may also be employed.

Upon formation of the glass layer, heating is continued to approach themelting point of the glass layer so that plastic flow of the glass layerat the sharp aperture edges will occur to round off or dull such steepsurface contours. The underlying insulating layer maintains the formedpattern. The device then appears as shown in FIG. 5, the glass layerbeing indicated by the reference numeral 35.

The final step in the present invention process is metalizing in thenormal manner, the device then appearing as shown in FIG. 6. Due to therounded edges of the doped glass layer 35, there are no stress pointscreated at the aperture edges and the films 30 and 31 are smooth andwithout cracks.

Although the present invention process has been described with a certaindegree of particularity in accordance with the presently preferredembodiment, the present disclosure has been made only by Way of exampleand that various changes may be resorted to without departing from thespirit and the scope of the invention as hereinafter claimed. Forexample, the desired doped glass may be formed by heating in anatmosphere containing atoms of the glass former, with or without priordeposition of the glass former, or by doping the surface of the siliconoxide glass layer prior to forming the apertures. The etched holes toconnect to the source and drain may be formed before or after theformation of layer 35.

I claim:

1. In the fabrication of a field effect semiconductor device wherein aninsulating layer is established on the surface of a body ofsemiconductor material, and having abrupt surface contours over which isestablished, at least in part, an interconnect film, the improvementcomprising: prior to forming said interconnect film, heating of saidinsulating layer in the presence of a glass former to cause controlledplastic flow of said glass at the abrupt surface contours to smooth saidcontours and not substantially adversely affect said devices.

2. The fabrication of a semiconductor device as defined in Claim 1wherein said heating is to a temperature that maintains any patternformed by said insulating layer.

3. The fabrication of a semiconductor device as defined in Claim 2wherein said body of semiconductor material is substantially unaffectedby said heating.

4. The fabrication of a semiconductor device as defined in Claim 3wherein said insulating layer comprises silicon oxide.

5. The fabrication of a semiconductor device as defined in Claim 4wherein atoms of said glass formers are deposited upon said oxide layerprior to heating of said oxide layer.

6. The fabrication of a semiconductor device as defined in Claim 4wherein said glass former forms a glass layer having a melting pointlower than said oxide.

7. The fabrication of a semiconductor device as defined in Claim 4wherein said oxide layer is heated in an atmosphere containing atoms ofsaid glass former.

8. The fabrication of a semiconductor device as defined in Claim 4,wherein an oxide layer containing atoms of said glass former isestablished on said silicon oxide layer prior to formation of saidsurface contours.

9. The fabrication of a semiconductor device as defined in Claim 1wherein said glass former is phosphorus.

10. The fabrication of a semiconductor device as defined in Claim 9wherein said semiconductor device is a silicon gate field effecttransistor, said body of semiconductor material being silicon.

11. The fabrication of a semiconductor device as defined in Claim 9wherein said phosphorus atoms are pyrolytically deposited upon saidoxide layer.

12. The fabrication of a semiconductor device as defined in Claim 4,wherein said oxide layer is heated in a phosphorus atom containingatmosphere.

13. The fabrication of a semiconductor device as defined in Claim 4wherein a phosphorus doped oxide layer is established on said siliconoxide layer prior to formation of said aperture.

14. The fabrication of a semiconductor device as defined in Claim 4wherein said surface contours are apertures in the oxide which exposesemiconductor and said film is a conductive film.

15. The fabrication of a semiconductor device as defined in Claim 14wherein said conductive film is aluminum.

16. The fabrication of a semiconductor device as defined in Claim 1wherein a conductive film is formed under said insulating layer and saidsurface contours are the result of said insulating layer being formedover said underlying conductive film.

17. The fabrication of a semiconductor device as defined in Claim 16wherein said underlying conductive film is polycrystalline silicon.

18. In the fabrication of a field effect device, the method comprisingforming a thick field oxide over a portion of a silicon substrate;removing a portion of said thick oxide in areas wherein a field effectdevice is to be formed; forming a thin gate oxide in said areas wheresaid field efiect device is to be formed; forming a gate material oversaid thin gate oxide and exposing a portion of said substrate in thevicinity of said thick field oxide and said thin gate oxide and saidoverlying gate material; diffusing impurity into said exposed substrateto form source and drain regions; forming a glass layer over at least aportion of said device, said layer exposing said source and drainregions; heating said glass layer to smooth abrupt contours over whichsaid glass layer is formed and depositing a metal layer over a portionof said glass layer and to make contact with at least a portion of saidsource and drain regions and said gates.

19. The method defined in Claim 18 wherein said gate layer is silicon.

References Cited UNITED STATES PATENTS 3,340,445 9/1967 Scott, Jr. eta1. 3l7235 X 3,309,245 3/1967 Haenichen 317-235 X 3,247,428 4/1966 Perriet a1 ll7--2l2 X RALPH S. KENDALL, Primary Examiner US. Cl. X.R.

l56l7; 3l7-235 A, 234 R

